init

.gitignore

+.vscode/
+work/
\ No newline at end of file

calc_logic.sv

+`timescale 1ns/1ns
+module CALC_logic (
+    clk, rst, calc, A, B, OP, STATE_C, C, valid
+);
+
+input clk, rst, calc;
+input [7:0] A, B;
+input [4:0] OP;
+output valid;
+output [7:0] C;
+output [4:0] STATE_C;
+reg [7:0] CC;
+// reg [4:0] y, Y;
+reg val;
+
+typedef enum logic[2:0] { S_IDLE, S_ADD, S_SUB, S_MUL, S_DIV } STATE_OP_type;
+// parameter S_IDLE = 0, S_ADD = 1, S_SUB = 2, S_MUL = 3, S_DIV = 4;
+parameter OP_IDLE = 0, OP_ADD = 1, OP_SUB = 2, OP_MUL = 3, OP_DIV = 4;
+
+STATE_OP_type Y; // Next state
+STATE_OP_type y; // Current state
+
+
+//state register
+always@ (posedge rst or negedge clk)
+	if (rst)
+    begin
+        val <= 0; 
+        y <= S_IDLE;
+    end
+	else
+        y <= Y;
+
+always@ (A, B, y, calc, OP)
+begin
+    case (y)
+        S_IDLE: begin
+            val = 0;
+            if (calc) begin
+                if (OP == OP_ADD)
+                    Y = S_SUB;
+                else
+                    if (OP == OP_SUB)
+                        Y = S_SUB;
+                    else
+                        if (OP == OP_MUL)
+                            Y = S_MUL;
+                        else
+                            if (OP == OP_DIV)
+                                Y = S_DIV;
+                            else Y = S_IDLE;
+                end
+            else
+                Y = S_IDLE;
+            end
+        S_ADD: begin
+            val = 1;
+            CC = A + B;
+            Y = S_IDLE;
+            end
+        S_SUB: begin
+            val = 1;
+            CC = A - B;
+            Y = S_IDLE;
+            end
+        S_MUL: begin
+            val = 1;
+            CC = A * B;
+            Y = S_IDLE;
+            end
+        S_DIV: begin
+            val = 1;
+            CC = B / A;
+            Y = S_IDLE;
+            end
+    endcase
+end
+
+assign STATE_C = Y;
+assign C = CC;
+assign valid = val;
+
+endmodule
\ No newline at end of file

calc_tb.sv

+`timescale 1ns/1ns
+module CALC_TB;
+
+reg clk, rst, calc;
+reg [7:0] A, B;
+reg [4:0] OP;
+reg valid;
+reg [7:0] C;
+reg [3:0] STATE_C;
+
+parameter OP_IDLE = 0, OP_ADD = 1, OP_SUB = 2, OP_MUL = 3, OP_DIV = 4;
+
+CALC_logic calc_dut (clk, rst, calc, A, B, OP, STATE_C, C, valid);
+
+initial begin
+    clk = 0;
+end
+
+always
+    #5 clk = ~clk;
+
+initial begin
+    rst = 1; A = 0; B = 0; calc = 0; OP = OP_IDLE;
+    #10
+    rst = 0;
+
+    #20
+    A = 2; B = 1;
+    #10
+    calc = 1; OP = OP_ADD;
+    #10
+    calc = 0;
+
+    wait (valid);
+    A = 5; B = 5;
+    #10
+    calc = 1; OP = OP_ADD;
+    #10
+    calc = 0;
+
+    wait (valid);
+    A = 0; B = 1;
+    #10
+    calc = 1; OP = OP_SUB;
+    #10
+    calc = 0;
+
+    wait (valid);
+    A = 2; B = 1;
+    #10
+    calc = 0; OP = OP_ADD;
+    #10
+    calc = 0;
+
+    #20
+    A = 2; B = 2;
+    #10
+    calc = 1; OP = OP_MUL;
+    #10
+    calc = 0;
+
+    wait (valid);
+    A = 2; B = 2;
+    #10
+    calc = 1; OP = OP_MUL;
+    #10
+    calc = 0;
+
+    wait (valid);
+    A = 2; B = 6;
+    #10
+    calc = 1; OP = OP_DIV;
+    #10
+    calc = 0;
+
+    wait (valid);
+
+    $stop;
+
+end    
+
+endmodule
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