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Commit 2839c6f8 by trkall
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lab3 done

parent e5fdf377
Inline Side-by-side
Showing with 2490 additions and 60 deletions
Labware/Lab1_4C123/Lab1.uvguix.Tref
......@@ -90,28 +90,28 @@
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......@@ -1865,9 +1865,9 @@
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<Name>.\Lab1.c</Name>
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......
Labware/Lab2_4C123/EventRecorderStub.scvd 0 → 100644
<?xml version="1.0" encoding="utf-8"?>
<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
<component name="EventRecorderStub" version="1.0.0"/> <!--name and version of the component-->
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</events>
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Labware/Lab2_4C123/Lab2.c
......@@ -489,7 +489,7 @@ int main_step4(void){
OS_AddThreads(&Task2, &Task3, &Task4, &Task5);
// when grading change 1000 to 4-digit number from edX
TExaS_Init(GRADER, 1000); // initialize the Lab 2 grader
// TExaS_Init(LOGICANALYZER, 1000); // initialize the Lab 2 logic analyzer
//TExaS_Init(LOGICANALYZER, 1000); // initialize the Lab 2 logic analyzer
OS_Launch(BSP_Clock_GetFreq()/THREADFREQ); // doesn't return, interrupts enabled in here
return 0; // this never executes
}
......
Labware/Lab2_4C123/Lab2.uvguix.Tref 0 → 100644
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<v6Lto>0</v6Lto>
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
......@@ -347,6 +351,7 @@
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<uClangAs>0</uClangAs>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
......
Labware/Lab2_4C123/Listings/Lab2.map 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
Labware/Lab2_4C123/Listings/osasm.lst 0 → 100644
ARM Macro Assembler Page 1
1 00000000 ;/******************************************************
***********************/
2 00000000 ; OSasm.s: low-level OS commands, written in assembly
*/
3 00000000 ; Runs on LM4F120/TM4C123/MSP432
4 00000000 ; Lab 2 starter file
5 00000000 ; February 10, 2016
6 00000000 ;
7 00000000
8 00000000
9 00000000 AREA |.text|, CODE, READONLY, ALIGN=
2
10 00000000 THUMB
11 00000000 REQUIRE8
12 00000000 PRESERVE8
13 00000000
14 00000000 EXTERN RunPt ; currently running
thread
15 00000000 EXPORT StartOS
16 00000000 EXPORT SysTick_Handler
17 00000000 IMPORT Scheduler
18 00000000
19 00000000
20 00000000 SysTick_Handler ; 1) Saves R0-R3,R1
2,LR,PC,PSR
21 00000000 B672 CPSID I ; 2) Prevent interr
upt during switch
22 00000002
23 00000002 B662 CPSIE I ; 9) tasks run with
interrupts enabled
24 00000004 4770 BX LR ; 10) restore R0-R3
,R12,LR,PC,PSR
25 00000006
26 00000006 StartOS
27 00000006
28 00000006 B662 CPSIE I ; Enable interrupts
at processor level
29 00000008 4770 BX LR ; start first threa
d
30 0000000A
31 0000000A 00 00 ALIGN
32 0000000C END
Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M4 --apcs=interw
ork --depend=.\objects\osasm.d -o.\objects\osasm.o -I.\RTE\_Target -IC:\Users\T
ref\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include -IC:\Users\Tref\
AppData\Local\Arm\Packs\Keil\TM4C_DFP\1.1.0\Device\Include\TM4C123 --predefine=
"__EVAL SETA 1" --predefine="__UVISION_VERSION SETA 529" --predefine="_RTE_ SET
A 1" --predefine="TM4C123GH6PM SETA 1" --list=.\listings\osasm.lst osasm.s
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
.text 00000000
Symbol: .text
Definitions
At line 9 in file osasm.s
Uses
None
Comment: .text unused
StartOS 00000006
Symbol: StartOS
Definitions
At line 26 in file osasm.s
Uses
At line 15 in file osasm.s
Comment: StartOS used once
SysTick_Handler 00000000
Symbol: SysTick_Handler
Definitions
At line 20 in file osasm.s
Uses
At line 16 in file osasm.s
Comment: SysTick_Handler used once
3 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
External symbols
RunPt 00000000
Symbol: RunPt
Definitions
At line 14 in file osasm.s
Uses
None
Comment: RunPt unused
Scheduler 00000000
Symbol: Scheduler
Definitions
At line 17 in file osasm.s
Uses
None
Comment: Scheduler unused
2 symbols
339 symbols in table
Labware/Lab2_4C123/Listings/startup_tm4c123.lst 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
Labware/Lab2_4C123/Objects/Lab2.build_log.htm 0 → 100644
<html>
<body>
<pre>
<h1>Vision Build Log</h1>
<h2>Tool Versions:</h2>
IDE-Version: Vision V5.29.0.0
Copyright (C) 2019 ARM Ltd and ARM Germany GmbH. All rights reserved.
License Information: Trevor Kallaste, Tref O, LIC=----
Tool Versions:
Toolchain: MDK-Lite Version: 5.29.0.0
Toolchain Path: C:\Keil_v5\ARM\ARMCC\Bin
C Compiler: Armcc.exe V5.06 update 6 (build 750)
Assembler: Armasm.exe V5.06 update 6 (build 750)
Linker/Locator: ArmLink.exe V5.06 update 6 (build 750)
Library Manager: ArmAr.exe V5.06 update 6 (build 750)
Hex Converter: FromElf.exe V5.06 update 6 (build 750)
CPU DLL: SARMCM3.DLL V5.29.0.0
Dialog DLL: DCM.DLL V1.17.3.0
Target DLL: lmidk-agdi.dll
Dialog DLL: TCM.DLL V1.36.5.0
<h2>Project:</h2>
C:\Users\Tref\bes_labs_2020\Labware\Lab2_4C123\Lab2.uvprojx
Project File Date: 04/17/2020
<h2>Output:</h2>
*** Using Compiler 'V5.06 update 6 (build 750)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'
Build target 'Target'
assembling osasm.s...
compiling os.c...
compiling Lab2.c...
assembling startup_TM4C123.s...
compiling system_TM4C123.c...
compiling Profile.c...
compiling BSP.c...
linking...
Program Size: Code=13120 RO-data=2128 RW-data=204 ZI-data=5956
".\Objects\Lab2.axf" - 0 Error(s), 0 Warning(s).
<h2>Software Packages used:</h2>
Package Vendor: ARM
http://www.keil.com/pack/ARM.CMSIS.5.6.0.pack
ARM.CMSIS.5.6.0
CMSIS (Cortex Microcontroller Software Interface Standard)
* Component: CORE Version: 5.3.0
Package Vendor: Keil
http://www.keil.com/pack/Keil.TM4C_DFP.1.1.0.pack
Keil.TM4C_DFP.1.1.0
Texas Instruments Tiva C Series Device Support and Examples
* Component: Startup Version: 1.0.1
<h2>Collection of Component include folders:</h2>
.\RTE\_Target
C:\Users\Tref\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include
C:\Users\Tref\AppData\Local\Arm\Packs\Keil\TM4C_DFP\1.1.0\Device\Include\TM4C123
<h2>Collection of Component Files used:</h2>
* Component: ARM::CMSIS:CORE:5.3.0
* Component: Keil::Device:Startup:1.0.1
Include file: Device\Include\TM4C123\TM4C123.h
Source file: Device\Source\ARM\startup_TM4C123.s
Source file: Device\Source\system_TM4C123.c
Build Time Elapsed: 00:00:01
</pre>
</body>
</html>
Labware/Lab2_4C123/Objects/Lab2.htm 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
Labware/Lab2_4C123/Objects/Lab2.lnp 0 → 100644
--cpu=Cortex-M4 --fpu=SoftVFP
".\objects\lab2.o"
".\objects\osasm.o"
".\objects\os.o"
".\objects\bsp.o"
".\objects\profile.o"
".\texas.o"
".\objects\startup_tm4c123.o"
".\objects\system_tm4c123.o"
--ro-base 0x00000000 --entry 0x00000000 --rw-base 0x20000000 --entry Reset_Handler --first __Vectors --strict --summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols
--info sizes --info totals --info unused --info veneers
--list ".\Listings\Lab2.map" -o .\Objects\Lab2.axf
\ No newline at end of file
Labware/Lab2_4C123/Objects/Lab2_Target.dep 0 → 100644
Dependencies for Project 'Lab2', Target 'Target': (DO NOT MODIFY !)
CompilerVersion: 5060750::V5.06 update 6 (build 750)::ARMCC
F (.\Lab2.c)(0x5E9996D0)(--c99 -c --cpu Cortex-M4 -D__EVAL -g -O0 --apcs=interwork --split_sections --signed_chars -I ../inc -I.\RTE\_Target -IC:\Users\Tref\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include -IC:\Users\Tref\AppData\Local\Arm\Packs\Keil\TM4C_DFP\1.1.0\Device\Include\TM4C123 -D__UVISION_VERSION="529" -D_RTE_ -DTM4C123GH6PM -o .\objects\lab2.o --omf_browse .\objects\lab2.crf --depend .\objects\lab2.d)
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5D9B2678)
I (../inc/BSP.h)(0x57B9E054)
I (../inc/Profile.h)(0x575817E4)
I (Texas.h)(0x56D8570C)
I (../inc/CortexM.h)(0x56B6D6E6)
I (os.h)(0x57C71192)
F (.\osasm.s)(0x57BDF362)(--cpu Cortex-M4 --pd "__EVAL SETA 1" -g --apcs=interwork -I.\RTE\_Target -IC:\Users\Tref\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include -IC:\Users\Tref\AppData\Local\Arm\Packs\Keil\TM4C_DFP\1.1.0\Device\Include\TM4C123 --pd "__UVISION_VERSION SETA 529" --pd "_RTE_ SETA 1" --pd "TM4C123GH6PM SETA 1" --list .\listings\osasm.lst --xref -o .\objects\osasm.o --depend .\objects\osasm.d)
F (.\os.c)(0x57C71192)(--c99 -c --cpu Cortex-M4 -D__EVAL -g -O0 --apcs=interwork --split_sections --signed_chars -I ../inc -I.\RTE\_Target -IC:\Users\Tref\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include -IC:\Users\Tref\AppData\Local\Arm\Packs\Keil\TM4C_DFP\1.1.0\Device\Include\TM4C123 -D__UVISION_VERSION="529" -D_RTE_ -DTM4C123GH6PM -o .\objects\os.o --omf_browse .\objects\os.crf --depend .\objects\os.d)
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5D9B2678)
I (os.h)(0x57C71192)
I (../inc/CortexM.h)(0x56B6D6E6)
I (../inc/BSP.h)(0x57B9E054)
F (..\inc\BSP.c)(0x5C97D55C)(--c99 -c --cpu Cortex-M4 -D__EVAL -g -O0 --apcs=interwork --split_sections --signed_chars -I ../inc -I.\RTE\_Target -IC:\Users\Tref\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include -IC:\Users\Tref\AppData\Local\Arm\Packs\Keil\TM4C_DFP\1.1.0\Device\Include\TM4C123 -D__UVISION_VERSION="529" -D_RTE_ -DTM4C123GH6PM -o .\objects\bsp.o --omf_browse .\objects\bsp.crf --depend .\objects\bsp.d)
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5D9B2678)
I (..\inc\BSP.h)(0x57B9E054)
I (..\inc\../inc/tm4c123gh6pm.h)(0x5C62BC12)
F (..\inc\Profile.c)(0x57581976)(--c99 -c --cpu Cortex-M4 -D__EVAL -g -O0 --apcs=interwork --split_sections --signed_chars -I ../inc -I.\RTE\_Target -IC:\Users\Tref\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include -IC:\Users\Tref\AppData\Local\Arm\Packs\Keil\TM4C_DFP\1.1.0\Device\Include\TM4C123 -D__UVISION_VERSION="529" -D_RTE_ -DTM4C123GH6PM -o .\objects\profile.o --omf_browse .\objects\profile.crf --depend .\objects\profile.d)
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5D9B2678)
I (..\inc\../inc/tm4c123gh6pm.h)(0x5C62BC12)
F (.\texas.o)(0x57C71DF6)()
F (RTE\Device\TM4C123GH6PM\startup_TM4C123.s)(0x56BB7426)(--cpu Cortex-M4 --pd "__EVAL SETA 1" -g --apcs=interwork -I.\RTE\_Target -IC:\Users\Tref\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include -IC:\Users\Tref\AppData\Local\Arm\Packs\Keil\TM4C_DFP\1.1.0\Device\Include\TM4C123 --pd "__UVISION_VERSION SETA 529" --pd "_RTE_ SETA 1" --pd "TM4C123GH6PM SETA 1" --list .\listings\startup_tm4c123.lst --xref -o .\objects\startup_tm4c123.o --depend .\objects\startup_tm4c123.d)
F (RTE\Device\TM4C123GH6PM\system_TM4C123.c)(0x52539E14)(--c99 -c --cpu Cortex-M4 -D__EVAL -g -O0 --apcs=interwork --split_sections --signed_chars -I ../inc -I.\RTE\_Target -IC:\Users\Tref\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include -IC:\Users\Tref\AppData\Local\Arm\Packs\Keil\TM4C_DFP\1.1.0\Device\Include\TM4C123 -D__UVISION_VERSION="529" -D_RTE_ -DTM4C123GH6PM -o .\objects\system_tm4c123.o --omf_browse .\objects\system_tm4c123.crf --depend .\objects\system_tm4c123.d)
I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5D9B2678)
I (C:\Users\Tref\AppData\Local\Arm\Packs\Keil\TM4C_DFP\1.1.0\Device\Include\TM4C123\TM4C123.h)(0x530EE4E6)
I (C:\Users\Tref\AppData\Local\Arm\Packs\Keil\TM4C_DFP\1.1.0\Device\Include\TM4C123\TM4C123GH6PM.h)(0x550FD41C)
I (C:\Users\Tref\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\core_cm4.h)(0x5D25E516)
I (C:\Users\Tref\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_version.h)(0x5D25E516)
I (C:\Users\Tref\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_compiler.h)(0x5D25E516)
I (C:\Users\Tref\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_armcc.h)(0x5D25E516)
I (C:\Users\Tref\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\mpu_armv7.h)(0x5C8FA234)
I (C:\Users\Tref\AppData\Local\Arm\Packs\Keil\TM4C_DFP\1.1.0\Device\Include\TM4C123\system_TM4C123.h)(0x51B6D5F6)
Labware/Lab2_4C123/Objects/bsp.d 0 → 100644
.\objects\bsp.o: ..\inc\BSP.c
.\objects\bsp.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
.\objects\bsp.o: ..\inc\BSP.h
.\objects\bsp.o: ..\inc\../inc/tm4c123gh6pm.h
Labware/Lab2_4C123/Objects/lab2.d 0 → 100644
.\objects\lab2.o: Lab2.c
.\objects\lab2.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
.\objects\lab2.o: ../inc/BSP.h
.\objects\lab2.o: ../inc/Profile.h
.\objects\lab2.o: Texas.h
.\objects\lab2.o: ../inc/CortexM.h
.\objects\lab2.o: os.h
Labware/Lab2_4C123/Objects/os.d 0 → 100644
.\objects\os.o: os.c
.\objects\os.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
.\objects\os.o: os.h
.\objects\os.o: ../inc/CortexM.h
.\objects\os.o: ../inc/BSP.h
Labware/Lab2_4C123/Objects/osasm.d 0 → 100644
.\objects\osasm.o: osasm.s
Labware/Lab2_4C123/Objects/profile.d 0 → 100644
.\objects\profile.o: ..\inc\Profile.c
.\objects\profile.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
.\objects\profile.o: ..\inc\../inc/tm4c123gh6pm.h
Labware/Lab2_4C123/Objects/startup_tm4c123.d 0 → 100644
.\objects\startup_tm4c123.o: RTE\Device\TM4C123GH6PM\startup_TM4C123.s
Labware/Lab2_4C123/Objects/system_tm4c123.d 0 → 100644
.\objects\system_tm4c123.o: RTE\Device\TM4C123GH6PM\system_TM4C123.c
.\objects\system_tm4c123.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
.\objects\system_tm4c123.o: C:\Users\Tref\AppData\Local\Arm\Packs\Keil\TM4C_DFP\1.1.0\Device\Include\TM4C123\TM4C123.h
.\objects\system_tm4c123.o: C:\Users\Tref\AppData\Local\Arm\Packs\Keil\TM4C_DFP\1.1.0\Device\Include\TM4C123\TM4C123GH6PM.h
.\objects\system_tm4c123.o: C:\Users\Tref\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\core_cm4.h
.\objects\system_tm4c123.o: C:\Users\Tref\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_version.h
.\objects\system_tm4c123.o: C:\Users\Tref\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_compiler.h
.\objects\system_tm4c123.o: C:\Users\Tref\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\cmsis_armcc.h
.\objects\system_tm4c123.o: C:\Users\Tref\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include\mpu_armv7.h
.\objects\system_tm4c123.o: C:\Users\Tref\AppData\Local\Arm\Packs\Keil\TM4C_DFP\1.1.0\Device\Include\TM4C123\system_TM4C123.h
Labware/Lab2_4C123/RTE/RTE_Components.h → Labware/Lab2_4C123/RTE/_Target/RTE_Components.h
/*
* Auto generated Run-Time-Environment Component Configuration File
* Auto generated Run-Time-Environment Configuration File
* *** Do not modify ! ***
*
* Project: 'Lab2'
......@@ -17,4 +17,5 @@
#define CMSIS_device_header "TM4C123.h"
#endif /* RTE_COMPONENTS_H */
Labware/Lab2_4C123/os.c
......@@ -16,8 +16,13 @@ void StartOS(void);
tcbType tcbs[NUMTHREADS];
tcbType *RunPt;
int32_t Stacks[NUMTHREADS][STACKSIZE];
uint32_t task1Rate = 0;//rate for 1st task
uint32_t task2Rate = 0;//rate for 2nd task
void (*threadPt1)(void) = 0;//thread 1
void (*threadPt2)(void) = 0;//thread 2
int32_t Mail;
uint32_t mailData = 0;
uint64_t Rate = 0;
// ******** OS_Init ************
// Initialize operating system, disable interrupts
// Initialize OS controlled I/O: systick, bus clock as fast as possible
......@@ -30,11 +35,29 @@ void OS_Init(void){
// initialize any global variables as needed
//***YOU IMPLEMENT THIS FUNCTION*****
}
void SetInitialStack(int i){
//***YOU IMPLEMENT THIS FUNCTION*****
tcbs[i].sp = &Stacks[i][STACKSIZE-16]; // Thread stack pointer
Stacks[i][STACKSIZE-1] = 0x01000000; // Enable thumb bit in PSR
// Stack[i][STACKSIZE-2] is for PC
Stacks[i][STACKSIZE-3] = 0x14141414; // R14 (LR)
Stacks[i][STACKSIZE-4] = 0x12121212; // R12
Stacks[i][STACKSIZE-5] = 0x03030303; // R3
Stacks[i][STACKSIZE-6] = 0x02020202; // R2
Stacks[i][STACKSIZE-7] = 0x01010101; // R1
Stacks[i][STACKSIZE-8] = 0x00000000; // R0
Stacks[i][STACKSIZE-9] = 0x11111111; // R11
Stacks[i][STACKSIZE-10] = 0x10101010; // R10
Stacks[i][STACKSIZE-11] = 0x09090909; // R9
Stacks[i][STACKSIZE-12] = 0x08080808; // R8
Stacks[i][STACKSIZE-13] = 0x07070707; // R7
Stacks[i][STACKSIZE-14] = 0x06060606; // R6
Stacks[i][STACKSIZE-15] = 0x05050505; // R5
Stacks[i][STACKSIZE-16] = 0x04040404; // R4
}
//******** OS_AddThreads ***************
......@@ -51,6 +74,31 @@ int OS_AddThreads(void(*thread0)(void),
// initialize four stacks, including initial PC
//***YOU IMPLEMENT THIS FUNCTION*****
// initialize TCB circular list
tcbs[0].next = &tcbs[1];
tcbs[1].next = &tcbs[2];
if (thread3) {
tcbs[2].next = &tcbs[3];
tcbs[3].next = &tcbs[0];
} else {
tcbs[2].next = &tcbs[0];
}
// initialize RunPt, thread 0 will run first
RunPt = &tcbs[0];
// initialize stacks, including initial PC
SetInitialStack(0);
SetInitialStack(1);
SetInitialStack(2);
SetInitialStack(3);
Stacks[0][STACKSIZE-2] = (int32_t)(thread0);
Stacks[1][STACKSIZE-2] = (int32_t)(thread1);
Stacks[2][STACKSIZE-2] = (int32_t)(thread2);
Stacks[3][STACKSIZE-2] = (int32_t)(thread3);
return 1; // successful
}
......@@ -66,8 +114,7 @@ int OS_AddThreads3(void(*task0)(void),
// initialize RunPt
// initialize four stacks, including initial PC
//***YOU IMPLEMENT THIS FUNCTION*****
return 1; // successful
return OS_AddThreads(task0, task1, task2, 0);// returns 1 if succesful
}
//******** OS_AddPeriodicEventThreads ***************
......@@ -84,7 +131,11 @@ int OS_AddPeriodicEventThreads(void(*thread1)(void), uint32_t period1,
void(*thread2)(void), uint32_t period2){
//***YOU IMPLEMENT THIS FUNCTION*****
return 1;
threadPt1 = thread1;// sets 1st periodic task to thread1
task1Rate = period1;// set the period for 1st task
threadPt2 = thread2;// sets 2nd periodic task to thread2
task2Rate = period2;// set the period for 2nd task
return 1; //succesful
}
//******** OS_Launch ***************
......@@ -105,7 +156,15 @@ void Scheduler(void){ // every time slice
// run any periodic event threads if needed
// implement round robin scheduler, update RunPt
//***YOU IMPLEMENT THIS FUNCTION*****
Rate++;
if (Rate % task1Rate == 0)
threadPt1();
if (Rate % task2Rate == 0)
threadPt2();
RunPt = RunPt->next; // next in stack
}
// ******** OS_InitSemaphore ************
......@@ -115,7 +174,9 @@ void Scheduler(void){ // every time slice
// Outputs: none
void OS_InitSemaphore(int32_t *semaPt, int32_t value){
//***YOU IMPLEMENT THIS FUNCTION*****
long lCrit = StartCritical();
*semaPt = value;
EndCritical(lCrit);
}
// ******** OS_Wait ************
......@@ -125,7 +186,13 @@ void OS_InitSemaphore(int32_t *semaPt, int32_t value){
// Inputs: pointer to a counting semaphore
// Outputs: none
void OS_Wait(int32_t *semaPt){
DisableInterrupts();
while(*semaPt == 0){
EnableInterrupts(); // interrupts can occur here
DisableInterrupts();
}
*semaPt = *semaPt - 1;
EnableInterrupts();
}
// ******** OS_Signal ************
......@@ -136,7 +203,9 @@ void OS_Wait(int32_t *semaPt){
// Outputs: none
void OS_Signal(int32_t *semaPt){
//***YOU IMPLEMENT THIS FUNCTION*****
DisableInterrupts();
*semaPt = *semaPt + 1;
EnableInterrupts();
}
......@@ -150,7 +219,7 @@ void OS_Signal(int32_t *semaPt){
void OS_MailBox_Init(void){
// include data field and semaphore
//***YOU IMPLEMENT THIS FUNCTION*****
OS_InitSemaphore(&Mail, 0);
}
// ******** OS_MailBox_Send ************
......@@ -161,6 +230,10 @@ void OS_MailBox_Init(void){
// Errors: data lost if MailBox already has data
void OS_MailBox_Send(uint32_t data){
//***YOU IMPLEMENT THIS FUNCTION*****
long lCrit = StartCritical();
mailData = data;//copy data to mail's data field
EndCritical(lCrit);
OS_Signal(&Mail);//signal OS
}
......@@ -172,9 +245,15 @@ void OS_MailBox_Send(uint32_t data){
// Inputs: none
// Outputs: data retreived
// Errors: none
uint32_t OS_MailBox_Recv(void){ uint32_t data;
uint32_t OS_MailBox_Recv(void){
uint32_t data;
//***YOU IMPLEMENT THIS FUNCTION*****
return data;
OS_Wait(&Mail);//signal OS
long lCrit = StartCritical();
data = mailData; // read mail
EndCritical(lCrit);
return data;//return mail data
}
Labware/Lab2_4C123/osasm.s
......@@ -17,14 +17,34 @@
IMPORT Scheduler
SysTick_Handler ; 1) Saves R0-R3,R12,LR,PC,PSR
CPSID I ; 2) Prevent interrupt during switch
PUSH {R4-R11} ; 3) Save remaining regs r4-11
LDR R0, =RunPt ; 4) R0=pointer to RunPt, old thread
LDR R1, [R0] ; R1 = RunPt
STR SP, [R1] ; 5) Save SP into TCB
PUSH {R0,LR}
BL Scheduler
POP {R0,LR}
LDR R1, [R0] ; 6) R1 = RunPt, new thread
LDR SP, [R1] ; 7) new thread SP; SP = RunPt->sp;
POP {R4-R11} ; 8) restore regs r4-11
CPSIE I ; 9) tasks run with interrupts enabled
BX LR ; 10) restore R0-R3,R12,LR,PC,PSR
StartOS
LDR R0, =RunPt ; Load addr of RunPt into R0
LDR R1, [R0] ; Load value of RunPt into R1
LDR SP, [R1] ; Load thread's SP from TCB into CPU SP
POP {R4-R11} ; Pop R4 - R11 from new SP (SP now points to R0 location)
POP {R0-R3} ; Pop R0 - R3 from SP (SP now points to R12 location)
POP {R12} ; Pop R12 (SP now points to LR (R14))
ADD SP, SP, #4 ; Skip LR by incrementing SP (SP now points to PC)
; - LR is invalid since this is the initial run
POP {LR} ; Pop PC (R15) into LR (SP now points to PSR)
; - PC should have already been initialized to start of tasks function
; - Popping directly into LR means that task will run when we BX LR
ADD SP, SP, #4 ; Skip PSR by incr. SP (SP now points to bottom of tasks stack)
CPSIE I ; Enable interrupts at processor level
BX LR ; start first thread
......
Labware/Lab3_4C123/RTE/_Target/RTE_Components.h
/*
* Auto generated Run-Time-Environment Component Configuration File
* Auto generated Run-Time-Environment Configuration File
* *** Do not modify ! ***
*
* Project: 'Lab3'
......@@ -17,4 +17,5 @@
#define CMSIS_device_header "TM4C123.h"
#endif /* RTE_COMPONENTS_H */
Labware/Lab3_4C123/os.c
......@@ -11,22 +11,36 @@
// function definitions in osasm.s
void StartOS(void);
void static runperiodicevents(void);
#define NUMTHREADS 6 // maximum number of threads
#define NUMPERIODIC 2 // maximum number of periodic threads
#define STACKSIZE 100 // number of 32-bit words in stack per thread
#define FIFOSIZE 10 // can be any size
struct tcb{
int32_t *sp; // pointer to stack (valid for threads not running
struct tcb *next; // linked-list pointer
int32_t *blocked;
int32_t sleeping;
// nonzero if blocked on this semaphore
// nonzero if this thread is sleeping
//*FILL THIS IN****
};
struct ptcb{
uint32_t period;
uint32_t counter;
void (*thread)();
};
typedef struct ptcb ptcbType;
ptcbType periodicEvents[NUMPERIODIC];
typedef struct tcb tcbType;
tcbType tcbs[NUMTHREADS];
tcbType *RunPt;
int32_t Stacks[NUMTHREADS][STACKSIZE];
void (*periodicTask)(void) = 0;
uint32_t periodicRate = 0;//rate for a task
int events = 0;
// ******** OS_Init ************
// Initialize operating system, disable interrupts
......@@ -38,12 +52,32 @@ void OS_Init(void){
DisableInterrupts();
BSP_Clock_InitFastest();// set processor clock to fastest speed
// perform any initializations needed
BSP_PeriodicTask_Init(runperiodicevents, 1000, 1);
}
void SetInitialStack(int i){
// **Same as Lab 2****
}
if (i >= NUMTHREADS)// if i is bigger than the amount of threads
return;
tcbs[i].sp = &Stacks[i][STACKSIZE-16]; // Thread stack pointer
Stacks[i][STACKSIZE-1] = 0x01000000; // Enable thumb bit in PSR
// Stack[i][STACKSIZE-2] is for PC
Stacks[i][STACKSIZE-3] = 0x14141414; // R14 (LR)
Stacks[i][STACKSIZE-4] = 0x12121212; // R12
Stacks[i][STACKSIZE-5] = 0x03030303; // R3
Stacks[i][STACKSIZE-6] = 0x02020202; // R2
Stacks[i][STACKSIZE-7] = 0x01010101; // R1
Stacks[i][STACKSIZE-8] = 0x00000000; // R0
Stacks[i][STACKSIZE-9] = 0x11111111; // R11
Stacks[i][STACKSIZE-10] = 0x10101010; // R10
Stacks[i][STACKSIZE-11] = 0x09090909; // R9
Stacks[i][STACKSIZE-12] = 0x08080808; // R8
Stacks[i][STACKSIZE-13] = 0x07070707; // R7
Stacks[i][STACKSIZE-14] = 0x06060606; // R6
Stacks[i][STACKSIZE-15] = 0x05050505; // R5
Stacks[i][STACKSIZE-16] = 0x04040404; // R4
}
//******** OS_AddThreads ***************
// Add six main threads to the scheduler
......@@ -57,6 +91,36 @@ int OS_AddThreads(void(*thread0)(void),
void(*thread4)(void),
void(*thread5)(void)){
// **similar to Lab 2. initialize as not blocked, not sleeping****
// initialize TCB circular list
tcbs[0].next = &tcbs[1];
tcbs[1].next = &tcbs[2];
tcbs[2].next = &tcbs[3];
tcbs[4].next = &tcbs[5];
tcbs[5].next = &tcbs[0];
// initialize RunPt, thread 0 will run first
RunPt = &tcbs[0];
// initialize stacks, including initial PC
SetInitialStack(0);
Stacks[0][STACKSIZE-2] = (int32_t)(thread0); // PC
SetInitialStack(1);
Stacks[1][STACKSIZE-2] = (int32_t)(thread1);
SetInitialStack(2);
Stacks[2][STACKSIZE-2] = (int32_t)(thread2);
SetInitialStack(3);
Stacks[3][STACKSIZE-2] = (int32_t)(thread3);
SetInitialStack(4);
Stacks[4][STACKSIZE-2] = (int32_t)(thread4);
SetInitialStack(5);
Stacks[5][STACKSIZE-2] = (int32_t)(thread5);
return 1; // successful
}
......@@ -74,6 +138,11 @@ int OS_AddThreads(void(*thread0)(void),
// In Lab 3 this will be called exactly twice
int OS_AddPeriodicEventThread(void(*thread)(void), uint32_t period){
// ****IMPLEMENT THIS****
periodicEvents[events].thread = thread;
periodicEvents[events].period = period;
periodicEvents[events].counter = period;
events++;
periodicRate = period;
return 1;
}
......@@ -81,7 +150,25 @@ int OS_AddPeriodicEventThread(void(*thread)(void), uint32_t period){
void static runperiodicevents(void){
// ****IMPLEMENT THIS****
// **RUN PERIODIC THREADS, DECREMENT SLEEP COUNTERS
DisableInterrupts();
uint32_t i;
for(i = 0; i < events; i++)
{
periodicEvents[i].counter--;
if(periodicEvents[i].counter % periodicEvents[i].period == 0)
{
periodicEvents[i].thread();
periodicEvents[i].counter = periodicEvents[i].period;
}
}
for (i = 0; i < NUMTHREADS; i ++){
if (tcbs[i].sleeping > 0)
{
(tcbs[i].sleeping) = (tcbs[i].sleeping) - 1;
}
}
EnableInterrupts();
}
//******** OS_Launch ***************
......@@ -100,6 +187,10 @@ void OS_Launch(uint32_t theTimeSlice){
// runs every ms
void Scheduler(void){ // every time slice
// ROUND ROBIN, skip blocked and sleeping threads
RunPt = RunPt->next; // skip at least one
while((RunPt->sleeping)||(RunPt-> blocked)){
RunPt = RunPt->next; // find one not sleeping and not blocked
}
}
//******** OS_Suspend ***************
......@@ -121,6 +212,9 @@ void OS_Suspend(void){
void OS_Sleep(uint32_t sleepTime){
// set sleep parameter in TCB
// suspend, stops running
RunPt->sleeping = sleepTime;
OS_Suspend();
}
// ******** OS_InitSemaphore ************
......@@ -130,6 +224,9 @@ void OS_Sleep(uint32_t sleepTime){
// Outputs: none
void OS_InitSemaphore(int32_t *semaPt, int32_t value){
//***IMPLEMENT THIS***
DisableInterrupts();
(*semaPt) = value;
EnableInterrupts();
}
// ******** OS_Wait ************
......@@ -140,6 +237,14 @@ void OS_InitSemaphore(int32_t *semaPt, int32_t value){
// Outputs: none
void OS_Wait(int32_t *semaPt){
//***IMPLEMENT THIS***
DisableInterrupts();
(*semaPt) = (*semaPt) - 1;
if((*semaPt) < 0){
RunPt->blocked = semaPt; // reason it is blocked
EnableInterrupts();
OS_Suspend(); // run thread switcher
}
EnableInterrupts();
}
// ******** OS_Signal ************
......@@ -150,6 +255,17 @@ void OS_Wait(int32_t *semaPt){
// Outputs: none
void OS_Signal(int32_t *semaPt){
//***IMPLEMENT THIS***
tcbType *pt;
DisableInterrupts();
(*semaPt) = (*semaPt) + 1;
if((*semaPt) <= 0){
pt = RunPt->next; // search for a thread blocked on this semaphore
while(pt->blocked != semaPt){
pt = pt->next;
}
pt->blocked = 0; // wakeup this one
}
EnableInterrupts();
}
#define FSIZE 10 // can be any size
......@@ -166,6 +282,9 @@ uint32_t LostData; // number of lost pieces of data
// Outputs: none
void OS_FIFO_Init(void){
//***IMPLEMENT THIS***
PutI = GetI = 0; // Empty
OS_InitSemaphore(&CurrentSize, 0);
LostData = 0;
}
// ******** OS_FIFO_Put ************
......@@ -176,8 +295,16 @@ void OS_FIFO_Init(void){
// Outputs: 0 if successful, -1 if the FIFO is full
int OS_FIFO_Put(uint32_t data){
//***IMPLEMENT THIS***
if(CurrentSize == FIFOSIZE){
LostData++;
return -1; // full
} else{
Fifo[PutI] = data; // Put
PutI = (PutI+1)%FIFOSIZE;
OS_Signal(&CurrentSize);
return 0; // success
}
}
......@@ -187,10 +314,14 @@ int OS_FIFO_Put(uint32_t data){
// do block if empty
// Inputs: none
// Outputs: data retrieved
uint32_t OS_FIFO_Get(void){uint32_t data;
uint32_t OS_FIFO_Get(void){
uint32_t data;
//***IMPLEMENT THIS***
OS_Wait(&CurrentSize); // block if empty
data = Fifo[GetI]; // get
GetI = (GetI+1)%FIFOSIZE; // place to get next
return data;
}
......
Labware/Lab3_4C123/osasm.s
......@@ -20,13 +20,31 @@
SysTick_Handler ; 1) Saves R0-R3,R12,LR,PC,PSR
CPSID I ; 2) Prevent interrupt during switch
;YOU IMPLEMENT THIS (same as Lab 2)
PUSH {R4-R11} ; 3) Save remaining regs r4-11
LDR R0, =RunPt ; 4) R0=pointer to RunPt, old thread
LDR R1, [R0] ; R1 = RunPt
STR SP, [R1] ; 5) Save SP into TCB
PUSH {R0,LR}
BL Scheduler
POP {R0,LR}
LDR R1, [R0] ; 6) R1 = RunPt, new thread
LDR SP, [R1] ; 7) new thread SP; SP = RunPt->sp;
POP {R4-R11} ; 8) restore regs r4-11
CPSIE I ; 9) tasks run with interrupts enabled
BX LR ; 10) restore R0-R3,R12,LR,PC,PSR
StartOS
;YOU IMPLEMENT THIS (same as Lab 2)
LDR R0, =RunPt ; Load addr of RunPt into R0
LDR R1, [R0] ; Load value of RunPt into R1
LDR SP, [R1] ; Load thread's SP from TCB into CPU SP
POP {R4-R11} ; Pop R4 - R11 from new SP (SP now points to R0 location)
POP {R0-R3} ; Pop R0 - R3 from SP (SP now points to R12 location)
POP {R12} ; Pop R12 (SP now points to LR (R14))
ADD SP, SP, #4 ; Skip LR by incrementing SP (SP now points to PC)
; - LR is invalid since this is the initial run
POP {LR} ; Pop PC (R15) into LR (SP now points to PSR)
; - PC should have already been initialized to start of tasks function
; - Popping directly into LR means that task will run when we BX LR
ADD SP, SP, #4 ; Skip PSR by incr. SP (SP now points to bottom of tasks stack)
CPSIE I ; Enable interrupts at processor level
BX LR ; start first thread
......
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